The present invention relates in general to bus architectures in data processing systems and in particular to connectors employed with PCI bus architecture. Still more particularly, the present invention relates to providing an improved connector to be employed in a PCI bus architecture utilizing differential signaling.
Even more specifically, the present invention describes Split Pin connector technology which provides significantly higher frequency and higher frequency capability to the board level; resulting from the fact that the Split Pin and Split Via halves are closer together.
Data processing systems typically experience data bottlenecks under older input/output (I/O) standard architectures, such as the Industry Standard Architecture (ISA) and Extended Industry Standard Architecture (EISA). These bottlenecks arise when data transfers are unable to keep pace with the requirements of a processing unit or other component within the data processing system. Alternative I/O architectures have been developed to eliminate such bottlenecks by providing higher bandwidth buses. One such alternative is the peripheral component interconnect (PCI) local bus, a high performance 32-bit or 64-bit bus with multiplexed address and data lines. The mechanical, electrical and operational characteristics for the current PCI local bus standard may be found in PCI Local Bus Specifications, Revision 2.1 (xe2x80x9cthe current PCI specificationsxe2x80x9d), available from the PCI Special Interest Group in Portland, Oreg. The current PCI specifications and/or variants are expected to be employed in data processing systems for a considerable time into the future.
The PCI local bus specifications provide a processor independent interface to add-on boards, also commonly referred to as expansion cards or adaptors. However, because of AC switching characteristic limitations, a PCI bus is typically limited in both data transfer rate and fan-out (number of adaptor slots supported). Data transfer rate and fan-out in a PCI bus are interdependent such that achieving an increase in one generally results in a decrease in the other. The current 33 MHz 64-bit PCI architecture definition provides a peak data transfer rate of 264 M/s and supports up to four slots per PCI I/O bus when operated at 33 MHz. This data rate is slow for many performance adaptors under contemporary workstation requirements. The current 66 MHz PCI architecture definition provides a peak data transfer rate of 528 M/s, but only supports up to two slots per PCI I/O bus when operated at 66 MHz. This fan-out is extremely restrictive, limiting the usefulness of the 66 MHz PCI architecture.
A high performance, general purpose parallel I/O bus similar to PCI, but with better performance and fan-out than provided by the current 66 MHz PCI definition, may be provided. The enhanced bus architecture builds upon the current 66 MHz PCI architecture but is not backward-compatible with existing PCI bus architecture specifications since the connectors employed for the existing PCI bus architecture cannot be employed for the enhanced bus architecture. It would, therefore, be desirable to provide connectors supporting the enhanced architecture.
It is, therefore, one objective of the present invention to provide an improved bus architecture enabling higher frequency and performance capability for data processing. It is yet another objective of the present invention to provide an improved connector employed with the enhanced bus architecture described, enabling higher frequency and performance capability.
Yet another object of the present invention to provide an improved connector to be employed in an enhanced bus architecture utilizing differential signaling. The connector may include both a 32-bit and a 64-bit connector. The foregoing objects are achieved as is now described.
There is a need for a higher frequency performance electrical connector that maintains the high density of present day connectors such as D-Shell 9 or 25 pin, with 2 mm or 0.100 inch center pin density connectors. Any standard connector currently can be made into a 500-1000 MHz or higher clock-rate data connector with the system of the current invention.
Specifically, the present invention is related to a system for connecting signal pins between two PCB""s. The various pins in the connector are typically separated by 0.100 inches. The conventional method of connecting differential signal pairs between two PCB""s uses two pins and each pin would typically be separated by 0.100 inches.
The present invention provides a modified pin that can be used to replace the pin in a standard connector. This modified pin (xe2x80x9cSplit Pinxe2x80x9d) will connect a differential signal pair on one printed circuit board (xe2x80x9cPCBxe2x80x9d), cable or other transmission medium to its mating differential signal pair on a second PCB, cable or other transmission medium. This concept is called differential pin capability.
Still another object of the present invention, to provide an improved connector to be employed in an enhanced bus architecture utilizing differential signaling connectors, includes the use of both a 32-bit and a 64-bit connector and Split Vias.
The foregoing objects are achieved as is now described. The above, as well as additional objects, features and advantages of the present invention will become apparent in the following detailed written description.